1. Field of the Invention
This invention relates to semiconductor devices and in particular to the processes used to fabricate them.
2. Description of the Prior Art
The process for fabricating conventional CMOS (Complementary Metal Oxide Semiconductor) semiconductor devices is well known and includes the steps of creating a gate dielectric layer, depositing polysilicon gate electrode material, patterning the polysilicon/dielectric gate stack into the gate electrode, implanting a drain extension implant, creating sidewall insulator structures (spacers), implanting a source/drain implant, and providing a heat treatment to diffuse and electrically activate the implanted layers. The implants can be of n-type or p-type dopants, for the formation of N-channel or P-channel devices respectively.
There are various technical issues related to conventional CMOS processes as technology scaling progresses with regard to the doping of the gate electrode. First, as the gate dielectric thickness is scaled down, the field intensity at the gate electrode/gate dielectric interface increases with the result that the gate electrode experiences depletion of charge starting at the dielectric interface. This condition is undesirable because it has the effect of increasing the effective gate dielectric thickness, and modulating the threshold voltage. Further, there is a competing issue that attempts to increase the doping of the gate electrode at the electrode/dielectric interface which enhances the risk of dopant diffusion through the gate dielectric and into the channel, particularly for boron doped gates. Dopant penetration of the gate dielectric is undesirable because it changes the threshold voltage. The device is sensitive to dopant penetration of the gate dielectric because the doping concentration in the channel region under the gate is low; therefore small amounts of dopant diffusing through the gate dielectric have significant effects.
There are two unit processes involved in the gate doping processes that interact to determine the extent of gate depletion and gate dielectric penetration. The first is the ion implant which provides the dopant atoms, and the second is the heat treatment, or annealing, needed to activate the implanted dopant, and which also diffuses the dopant through the gate material. The ion implant energy is chosen to be low, even though this compromises productivity, to ensure that no dopant is implanted through the gate oxide, since the underlying channel region is doped with a low concentration. This requires that the dopant be diffused through the gate layer to provide dopant at the gate electrode/gate dielectric interface where it is needed to prevent gate depletion. However, the gate material is usually polysilicon, which has very nonuniform diffusion characteristics. As such, there is very fast diffusion down to the grain boundaries in the polysilicon, so some dopant reaches the gate electrode/gate dielectric interface quickly, yet most of the dopant still needs to diffuse to fully dope the polysilicon grains and achieve high conductivity. The grain boundary dopant at the gate electrode/gate dielectric interface is then a risk for gate dielectric penetration as the heat treatment continues. This risk is increased as the heat treatment goes to higher temperatures and longer times. There are practical limits to the reduction of time/temperature for the gate electrode anneal, due to the need to diffuse the dopant to the gate electrode/gate dielectric interface and the need to electrically activate the implanted dopant, for example, as disclosed in M. Kase, et al. “FEOL Technologies for Fabricating High Performance Logic and System LSI of 100 nm node, 12th International Conference on Ion Implantation Technology Proceedings, 1998, p. 91.
The technologies that have been proposed to address these issues include oxynitride gate dielectric, SiGe gate electrode material, and metal gate electrode materials. The oxynitride gate dielectric is useful for the reduction of the boron penetration through the gate oxide, but does not help with the gate depletion effect. The SiGe gate material also reduces boron diffusion and thus helps with gate penetration while increasing the effective doping concentration, which also helps with the gate depletion. The problem is that the SiGe gate material degrades the NMOS characteristics and thus requires complex selective technologies to achieve a full CMOS solution. The metal gate approach solves the boron penetration problem (no boron to diffuse) and the gate depletion issue (near infinite charge concentration) but makes setting the threshold voltage for, NMOS and PMOS simultaneously very difficult. The metal gate approach also has significant challenges in process integration; since the metal layers are not physically stable at the high temperatures of the heat treatments required for implant activation, such as required by the source and drain regions.
The conventional device faces other limiting factors as technology scales. With continued scaling, for example <0.1 um technology, the conventional device suffers from the need to provide sufficient gate overlap of the drain extension region to ensure high performance operation. In particular, the extrinsic series resistance becomes a limiting factor as the overlap regions are scaled. A recent analysis, as reported by Ghani et al, Symposium VLSI Technology, pages 17-18, 2001, has shown that an asymmetric structure has the potential to allow further scaling while maintaining high performance device characteristics. However, the process used by Ghani, et al in the demonstration devices is very constraining relative to large-scale production requirements: the structure requires a tilt implant selectively on the source side and not the drain side. To manufacture devices with such a structure would require limiting the layout so that all sources are to one side and all drains to the other, making the circuit very large.
There is also a trend to form shallow semiconductor junctions. The requirement for shallow junctions is a direct result of the continued scaling of semiconductor technology wherein there is a constant progression to smaller devices. As the devices are made smaller, there are many features of the fabrication process that must be modified, or “scaled” in order to maintain proper functionality of the transistor and other circuit elements required. The impact on junction formation technology is that it is expected that the junction depth would scale as technology scales, that is, the junctions become shallower as the gate length becomes shorter. In this way, the transistor functionality is preserved.
There are difficulties with continuing the historical methods of scaling the junction depth. In particular, the conventional method of formation of such junctions is the use of ion implantation to introduce the dopant into the semiconductor substrate, followed by a heat treatment step to make the dopant atoms electrically active. To achieve shallower junctions, the ion implantation must be performed with lower energy, so that the atoms do not penetrate into the semiconductor substrate as far. In general, shallow junctions require an ion implant energy of less than 5 keV, while ultra-shallow junctions require ion implant energy of less than 1 keV (for boron implants). These implants have low productivity on a conventional implanter because they are in the regime where Child's Law applies; implants with energy of less than 10 keV. In this regime, the implanter's beam current is limited by space charge effects, with a maximum current that is proportional to the extraction voltage to the 3/2 power. The conventional means of increasing the productivity in this regime is to implement an acceleration/deceleration configuration for the implanter: the beam is extracted at high energy to avoid the space charge limit imposed by Childs Law, and then decelerated before the wafers to implant with the correct energy. While this method is able to increase productivity by around 2×, the deceleration beam has issues with energetic contamination and nonuniformity of implant results.
There are further issues with the conventional implant process for the formation of ultrashallow junctions in that the implant creates defect structures within the silicon implanted layer that pose more of an issue as the energy is reduced and the layer becomes shallower. First, the density of created defects increases quickly because the implanted volume of the substrate material is reduced as the implant is made shallow. Since the doses are either the same or increasing, the reduction of implant depth corresponds to an increase in both the density of implanted dopant and the implant defects. As the defect density increases, the probability of interaction increases dramatically, with the problem that combinations of defects make more complex defect structures which are very difficult to anneal. It may be noted that the high density of implanted dopant, boron for example, also increases the probability that dopant complex structures will form. This is particularly an issue when the dopant concentration exceeds the solid solubility, since the supersaturated dopant tends to precipitate into undesirable structures. For example, supersaturated boron tends to precipitate into silicon boride (SiB4), a structure which binds the boron into electrically inactive position, rendering that component of the boron implant completely ineffective. As the energy is reduced, more of the implanted dose resides in a region where the concentration is above the solubility, so the effectiveness of the implant decreases with energy.
The conventional process also places extreme constraints on the heat treatment, or anneal, used to make the implanted dopant electrically active. There is a strong conflict between the need to heat the substrate to high temperatures to effectively activate the implanted dopant versus the need to limit the temperature and time of the anneal to prevent diffusion. This conflict has lead to the development of a process called the spike anneal, where the temperature is ramped quickly to a peak temperature, and then immediately ramped down, such that the residence time at the maximum temperature approaches zero. Such an anneal is necessary for the formation of ultrashallow boron junctions to minimize the diffusion of boron.
It has been proposed to address some of these issues with the formation of ultrashallow junctions by implanting into a surface oxide layer and then diffusing through the oxide into the substrate to form the junction, for example, as discussed in Schmitz, et al, “Ultra-Shallow Junction Formation by Outdiffusion from Implanted Oxide” IEEE-IEDM '98, p 1009; and Schmitz, et al, “Shallow Junction Fabrication by Rapid Thermal Outdiffusion from Implanted Oxides” Proceedings of Advances in Rapid Thermal Processing, Electrochemical Society, Seattle Wash., 1999, p. 187. This approach has the advantage of reducing or eliminating the defect formation in the semiconductor substrate by placing most of the implant damage into the oxide layer. The method also relaxes the constraints on annealing because most of the diffusion is now through the oxide layer. The method has the disadvantage, though, that diffusion through oxide is generally slower than through silicon, for example, as discussed in Fair, “Physical Models of Boron Diffusion in Ultrathin Gate Oxides” J. Electrochem. Soc, 144, 1997, p. 708-717.
A further issue with the conventional process is the difficulty in avoiding implanting into an oxide while attempting to form an ultrashallow junction, for example, as discussed in Krull, et al, “The importance of the native oxide for sub-keV ion implants,” Proc. 12th International Conference on Ion Implant Technoloy—1998, p 1113, 1999. As technology scales and the implant energy is reduced, it becomes increasingly difficult to remove the surface oxide well enough that it does not interfere with the ion implant process. As discussed by Krull, et al, even a native oxide (oxide that forms on a silicon wafer just by exposure to air at room temperature) is thick enough that a boron implant with energy of 250 eV places most of the atoms into the oxide (1.5 nm) rather than into the silicon as intended. Since the native oxide forms at room temperature in air, extreme measures are required to implant into truly bare substrates, such as an in-situ oxide strip inside the vacuum system of the ion implanter. There are no production implanters with such capability. Absent the ability to implant into truly bare substrates, the production solution must involve controlling the thickness of oxide present and implanting into that oxide. Such a process will be required to provide production level repeatability.